Design of the vector floating-point unit with high area efficiency

Abstract With the development of information age, there is an increasing trend towards mixed precision and vector operations in floating point arithmetic. Traditional floating-point arithmetic usually implemented using multiple modules to ensure required speed. Still, this approach significantly increases area reduces efficiency, resulting wastage hardware resources. This paper focuses on optimizing speed improve area’s efficiency. The proposed unit designed can perform half-precision, single-precision, double-precision operations. Under TSMC 7 nm process, its maximum operating frequency increased by 5%–37%, reduced 33%–58%, efficiency 63%–144%.